Title:
【発明の名称】自動メモリ―・テスタ装置
Document Type and Number:
Japanese Patent JP2539889
Kind Code:
B2
Abstract:
Automatic memory tester apparatus for processing failure information of a memory under test (MUT) including a high speed pattern generator for providing digital test patterns to the MUT for storage of data at MUT addresses in the MUT, a failure processor for comparing outputs from the MUT with expected outputs to obtain failure information, and a fail map random access memory (RAM) having fail map addresses corresponding to the MUT addresses and connected to receive the failure information and store it at corresponding fail map addresses. The fail map addresses includes bits to address individual bits of multibit words. An address generator of the high speed pattern generator for randomly addresses and reads individual bits of the multibit words to provide a serial bit output for display. Relative positions of the display related to topical positions of associated memory elements on the MUT.
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Inventors:
MAAKU ANTON RITSUCHI
Application Number:
JP14035588A
Publication Date:
October 02, 1996
Filing Date:
June 07, 1988
Export Citation:
Assignee:
TERADYNE INC
International Classes:
G01R31/28; G11C29/00; G11C29/40; G11C29/56; G01R31/3193; G06F11/00; G06F11/277; G06F11/32; (IPC1-7): G11C29/00; G01R31/28
Domestic Patent References:
| JP626498A | ||||
| JP6111999A |
Attorney, Agent or Firm:
Kyozo Yuasa (4 outside)