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Title:
HOLDING SYSTEM OF FAULT INFORMATION
Document Type and Number:
Japanese Patent JPS58130661
Kind Code:
A
Abstract:

PURPOSE: To realize a means to hold assuredly the fault information although the power supply of a faulty device is cut off, by providing a means which receives the fault information given from the faulty device and then holds a fault display signal by means of a power supply which is independent of the faulty device.

CONSTITUTION: The output of a delaying circuit 51 is fed to a terminal CL of a flip-flop 71 via a gate 16 in a conductive state. Therefore the flip-flop 71 via a gate 16 in a conductive state. Therefore the flip-flop 71 is set on the basis of the fault information (a) which is fed to a terminal D and then delivers the held fault information (b) through a terminal Q. The information (b) energizes a held fault information display 91 via a driver 81 and is also fed to a terminal S of a flip-flop 120 via a gate 10 and a delaying circuit 110 which has about 200mm delay time. Thus the flip-flop 120 is set. As a result, gates 6l∼6n are blocked by the output supplied from the terminal Q of the flip-flop 120 and after a delay time. Then the setting due to the fault information produced thereafter is prevented for flip-flops 7l∼7n.


Inventors:
IGI YOUZOU
UCHIDA YUKIO
Application Number:
JP1982000012995
Publication Date:
August 04, 1983
Filing Date:
January 29, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04M3/22; G06F11/34; H04M3/08; (IPC1-7): G06F11/32; H04M3/22
Domestic Patent References:
JPS5146007A1976-04-20
JPS4892000A1973-11-29