Title:
多層セラミック基板の内蔵コンデンサの容量値調整方法、ならびに多層セラミック基板およびその製造方法
Document Type and Number:
Japanese Patent JP4720829
Kind Code:
B2
Abstract:
In a multilayer ceramic substrate, without significantly changing the insulation resistance between capacitor electrodes and the Q value of a capacitor, there is provided a method for performing laser trimming to obtain a precise capacitance value of a built-in capacitor. In a multilayer ceramic substrate (1) having a built-in capacitor (2) formed in a ceramic laminate (6) composed of a plurality of ceramic layers (3 to 5) laminated to each other, the built-in capacitor (2) being formed of a first capacitor electrode (7), a second capacitor electrode (8), and the dielectric glass ceramic layer (4), the capacitance value of the built-in capacitor (2) is regulated by performing laser trimming of the first capacitor electrode (7). In this case, the dielectric glass ceramic layer (4) is formed of a TiO 2 -based dielectric glass ceramic layer in which the content of dielectric grains including TiO 2 is 10 to 35 percent by volume.
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Inventors:
Satoshi Oga
Yasutaka Sugimoto
Yasutaka Sugimoto
Application Number:
JP2007555856A
Publication Date:
July 13, 2011
Filing Date:
November 21, 2006
Export Citation:
Assignee:
MURATA MANUFACTURING CO.,LTD.
International Classes:
H01G4/12; H01G4/30; H01G4/232; H05K3/46
Domestic Patent References:
| JPH1055933A | 1998-02-24 | |||
| JPH11310455A | 1999-11-09 | |||
| JP2002097072A | 2002-04-02 | |||
| JP2005217170A | 2005-08-11 | |||
| JP2004311534A | 2004-11-04 | |||
| JP2005328396A | 2005-11-24 |
Foreign References:
| WO2005082806A1 | 2005-09-09 |
Attorney, Agent or Firm:
Masaaki Koshiba