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Title:
集積回路によって発生された周波数を調整する方法
Document Type and Number:
Japanese Patent JP4944288
Kind Code:
B2
Abstract:
The present invention relates to a system and method for compensating IC parameters. According to an embodiment of the present invention, a die of an IC wafer is coupled with a compensation circuit that classifies the die into various types. Examples of types include fast, typical, and slow. The assigned type may be used in a special oscillator that compensates for variations from a die to a predetermined criteria. According to an embodiment of the present invention, a slow die directs a signal that moves through a relatively short path, a fast die directs a signal that moves through a relatively long path, and a typical die directs a signal that moves through a relatively medium length path in the compensation circuit. Accordingly, each die on a wafer may be coupled with a compensation circuit such that the compensation circuit selects a path of a circuit that adjusts the frequency produced by the dies to produce a batch of ICs that would meet the predetermined criteria for the vast majority of the dies. A large number of useable Ics would be produced by adjusting the frequency produced by the ICs which would conventionally not meet the predetermined criteria to a frequency that does meet the predetermined criteria.

Inventors:
James M Pissione
Application Number:
JP2000092099A
Publication Date:
May 30, 2012
Filing Date:
March 29, 2000
Export Citation:
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Assignee:
Infineon Technologies North America Corp.
International Classes:
G01R31/26; G01R23/15; G01R31/319; G06F1/08; H03K5/135; H03L1/00
Domestic Patent References:
JP8079060A
JP59167813A
JP4119008A
JP7046120A
JP11041095A
JP11177399A
Attorney, Agent or Firm:
Toshio Yano
Takuya Kuno
Einzel Felix-Reinhard