膜パターンの形成方法 - Semiconductor Energy Laboratory Co., Ltd.

Title:

膜パターンの形成方法

Document Type and Number:

Japanese Patent JP5093985

Kind Code:

B2

Abstract:

To provide a manufacturing method for a substrate having a film pattern including an insulating film, a semiconductor film, a conductive film, and the like, by simple steps, and a method for forming an insulating film such as an interlayer insulating film, a planarizing film, and a gate insulating film, a conductive film such as wiring, an electrode and a terminal, films of respective areas of a semiconductor element such as a semiconductor film, a good mask pattern, and a contact hole, and further to propose a manufacturing method for a semiconductor device which has low cost with high throughput and yield.

After a mask pattern which has low wettability on a substrate is formed, a material which has high wettability is applied or discharged on an outer edge of the first mask pattern, thereby a substrate having the film pattern is formed.

Inventors:

Shinji Maekawa
Genki Fujii
Yuko Shiroguchi
Masafumi Morisue

Application Number:

JP2005007477A

Publication Date:

December 12, 2012

Filing Date:

January 14, 2005

Export Citation:

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Assignee:

Semiconductor Energy Laboratory Co., Ltd.

International Classes:

B05D1/26; G02F1/13; B05D1/32; B05D3/02; H01L21/28; H01L21/288; H01L21/3205; H01L21/336; H01L21/768; H01L29/786; H01L51/00; H01L51/05

Domestic Patent References:

JP2003282559A
JP2002237383A
JP2003124215A
JP2003124210A
JP2002164635A
JP2002311592A

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