Title:
ECHO CANCELLER
Document Type and Number:
Japanese Patent JP3236226
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the arithmetic operation volume at initial stage of convergence by providing an adaptive filter part to generate a false echo signal, an inner state updating part, a block size control part to sequentially output to the adaptive filter part and an adder.
SOLUTION: A far end input signal Rin and a near end input signal Sin are monitored by the block size control part 101 and an operation mode is decided from a relation between both signals. When initialization is performed, a tap number control signal BC whose value from the control part 101 shows 1 is outputted to an inner state updating part 102 and the adaptive filter part 103. The updating part 102 forms a gain vector and an inner state variable matrix at current time by a specified equation and a tap coefficient vector at current time in the filter part 103. And the false echo signal ER at current time is formed by the specific equation in the filter part 103 and an echo cancellation is performed in the adder R by subtracting the false echo signal ER.
Inventors:
Yoshihiro Ariyama
Masasuke Takada
Masasuke Takada
Application Number:
JP24022096A
Publication Date:
December 10, 2001
Filing Date:
September 11, 1996
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
H03H21/00; H03H17/00; H04B3/23; (IPC1-7): H04B3/23; H03H17/00; H03H21/00
Domestic Patent References:
| JP7202766A | ||||
| JP88691A | ||||
| JP786933A |
Attorney, Agent or Firm:
Nobuyuki Kudo