ハイブリッド・データ修復システム

Title:

ハイブリッド・データ修復システム

Document Type and Number:

Japanese Patent JP4309754

Kind Code:

B2

Abstract:

In a data recovery circuit, multiple slicer outputs of incoming data for each data bit, e.g., one or more slicer outputs taken at or near the center of the eye and one or more slicer outputs taken at or near the leading edge and/or trailing edge of the eye, are processed in a manner that reduces the bit-error rate relative to the prior art. The data recovery circuit may be combined with state-of-the-art clock recovery circuits to yield improved clock and data recovery (CDR) circuits.

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Inventors:

Nuriard. Doug Devilen
Erol Eleil Mats

Application Number:

JP2003420251A

Publication Date:

August 05, 2009

Filing Date:

December 18, 2003

Export Citation:

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Assignee:

Agia Systems Incorporated

International Classes:

H04L1/00; H04L25/03; H04L7/033; H04L25/06

Domestic Patent References:

JP2000196575A
JP9083500A
JP2000031951A

Attorney, Agent or Firm:

Masao Okabe
Nobuaki Kato
Kazuo
Shinichi Usui
Ikuo Fujino
Takao Ochi
Teruhisa Motomiya
Norimichi Takanashi
Asahi Shinmitsu
Seiichiro Takahashi
Koji Yoshizawa

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