Title:
HYBRID INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3203377
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the power loss by connecting each base, emitter and collector of two power transistor mounting parts on a metal base printed board in parallel, and making collector heat sinks adhere to each other with eutectic solder in between, so that an emitter resistor inserted between emitter electrodes is minimized.
SOLUTION: Eutectic solder 21 is assigned between collector heat sinks 5 and 11 of the first and second power transistor mounting parts 23 and 24. And, in a metal base print board 1, a copper foil pattern is formed on a metal base such as aluminum, etc., with an insulation layer in between, and a chip circuit component such as a CR chip, etc., is placed on the pattern. And, an emitter resistor 14 is formed with the use of the copper foil connected to the emitter of the first power transistor chip 2. An emitter resistor 15 is formed with the use of the copper foil connected to the emitter of the second power transistor chip 8.
Inventors:
Katsuhiko Higashiyama
Application Number:
JP22539595A
Publication Date:
August 27, 2001
Filing Date:
September 01, 1995
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L29/78; H01L25/00; (IPC1-7): H01L25/00
Domestic Patent References:
| JP62133745A | ||||
| JP1143287U |
Attorney, Agent or Firm:
Mitsutake Murayama