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Patent Searching and Data


Title:
HYBRID INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH03148894
Kind Code:
A
Abstract:

PURPOSE: To reduce cost by forming a metallic thin film wiring layer from the laminated films of a copper thin-film wiring layer, a metallic thin-film barrier layer and an aluminum thin-film wiring layer.

CONSTITUTION: A metallic thin-film adhesive layer 21 such as a Cr film is shaped onto an insulating layer 9, and a copper thin-film wiring layer 22, a metallic thin-film barrier layer 23 and an Al thin-film wiring layer 24 are formed successively onto the layer 21 through a continuous sputtering method, etc. The exposed section of the layer 22 and the electrode terminal of a chip part 3 are bonded and connected by a conductive adhesive material layer 5, and the bonding pads 24 of the layer 24 and the electrode terminal sections of an IC bare chip 4 and the pads 24 of the layer 24 and terminals 6 in a lead frame are connected through wire bonding. Accordingly, the wiring layers can be formed without completely using Au, thus reducing cost.


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Inventors:
TOSHIMA HIROAKI
MATSUZAKI TOSHIO
Application Number:
JP28811389A
Publication Date:
June 25, 1991
Filing Date:
November 06, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H05K1/18; H01L27/01; H05K1/09; H05K3/32; (IPC1-7): H01L27/01; H05K1/09; H05K1/18
Attorney, Agent or Firm:
Sadaichi Igita