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Title:
HYSTERESIS CIRCUIT
Document Type and Number:
Japanese Patent JPH0290066
Kind Code:
A
Abstract:

PURPOSE: To make it possible to constitute a circuit which can be designed easily and is characterized by low power consumption by combining detecting circuits at two high and low levels wherein input threshold levels are changed and an RSFF, and performing hysteresis operation.

CONSTITUTION: A high-level detecting circuit 2 and a low-level detecting circuit 3 which are connected to an input terminal 1 are circuits which detect the high side and the low side of the input signal levels, respectively. The threshold levels of the circuits are VTH and VTL, respectively. The output of the circuit 2 is connected to the -S signal terminal of an RSFF. The output of the circuit 3 is connected to the R signal input terminal of the RSFF. The Q signal terminal is connected to an output terminal 5. The circuit 2 and the circuit 3 of such a hysteresis circuit are composed of inverters 6 and 7, respectively. The outputs of the inverters are inputted into the -S and R terminals of the RSFF 4. The FF 4 is composed of an inverter 8 that is connected to the -S terminal and two NOR circuits 9 and 10. The Q signal terminal is connected to the output terminal 5.


Inventors:
YAZAWA AKIRA
Application Number:
JP24274988A
Publication Date:
March 29, 1990
Filing Date:
September 27, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
G01R19/165; H03K3/2893; (IPC1-7): G01R19/165; H03K3/295
Domestic Patent References:
JPS5928292A1984-02-14
JPS5775024A1982-05-11
JPS4745562A
JPS5568729A1980-05-23
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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