Title:
【発明の名称】最適なサイズの受信メモリを自動で選択するATMコントローラ
Document Type and Number:
Japanese Patent JP2970598
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce software processing at a CPU and frequency of the occurrence of under run by selecting a reception buffer memory in a suitable size corresponding to the cell rate of channel to be received. SOLUTION: A CPU 5 previously secures a reception buffer memory area for received data storage in a memory 6. The number of pointer areas 8, the number of data buffers 7 to be bundled in each pointer area 8 and the size of buffer 7 are set to be respectively different. When a cell is received, an ATM controller 3 sets a VPI/VCI value provided at its header part to a header table 3-2 and stores the value of timer 3-3 at such a point of time. By referring to the counter value of timer 3-3 and comparing it with a previous value, the cell rate of that channel is known. Corresponding to the interval time of cells, the ATM controller 3 selects the correspondent reception buffer memory.
Inventors:
OOTO YOSHINOBU
Application Number:
JP15772297A
Publication Date:
November 02, 1999
Filing Date:
May 30, 1997
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H04Q3/00; H04L12/28; H04L13/08; H04L47/43; H04L49/901; (IPC1-7): H04L12/28; H04L13/08
Domestic Patent References:
| JP7183888A | ||||
| JP4157943A | ||||
| JP6232893A | ||||
| JP8331164A | ||||
| JP193235A |
Attorney, Agent or Firm:
Asato Kato