Title:
【発明の名称】アクセスが制御されるマルチプロセッサ・システム・ブリッジ
Document Type and Number:
Japanese Patent JP2002518736
Kind Code:
A
Abstract:
A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. It also comprises a bridge control mechanism configured to be operable, in an operational mode to permit access by at least one of the first and second processing sets to bridge resources and to the device bus and, in an error mode, to prevent access by the processing sets to the device bus and to permit restricted access to at least one of the processing sets to at least predetermined bridge resources. By providing restricted access to selected parameters held in the bridge during an error mode, the bridge can act as a secure repository for information which can be used by the processing sets to investigate the error and hopefully to recover therefrom, while preventing I/O devices connected to device bus from being corrupted by a faulty processing set. Storage in the bridge provides for buffering data pending resolution of the error.
Inventors:
Laurinson, Stephen
Oilakin, Femi Ai
Garnet, Paul Jay
Oilakin, Femi Ai
Garnet, Paul Jay
Application Number:
JP2000555161A
Publication Date:
June 25, 2002
Filing Date:
June 03, 1999
Export Citation:
Assignee:
Sun Microsystems,Inc.
International Classes:
G06F11/00; G06F11/18; G06F11/22; G06F13/36; G06F13/40; G06F11/16; (IPC1-7): G06F11/18; G06F13/36
Attorney, Agent or Firm:
Masaki Yamakawa