Title:
【発明の名称】改善されたレール間性能を有するCMOS演算増幅器
Document Type and Number:
Japanese Patent JP3390172
Kind Code:
B2
Abstract:
A CMOS constant gain operational amplifier (20) has two differential input circuits (22, 24), each having a current source (40, 40A) and a compensation circuit (45, 45A). Each compensation circuit (45, 45A) dynamically tracks the common mode input voltage relative to a respective supply voltage and generates a respective tracking voltage that is used to modulate the current source of the respective differential input circuit. By modulating the current sources in accordance with the common mode input voltage, the input circuits are maintained in their saturation mode of operation over almost the entire rail-to-rail voltage range of the operational amplifier. The amplification stage circuit (27) also includes a dynamic bias adjustment circuit (95) that adjusts the bias of pull-down transistors (88, 90, 92, 94) in the presence of high speed input signal transients so as to keep the pull-down transistors in the amplification stage circuit in their normal, saturation mode of operation. As a result, the operational amplifier maintains virtually constant open loop gain throughout its entire operating range.
Inventors:
Fong, Edison
Nguyen, Ngheim
Nguyen, Ngheim
Application Number:
JP51914494A
Publication Date:
March 24, 2003
Filing Date:
February 16, 1994
Export Citation:
Assignee:
NATIONAL SEMICONDUCTOR CORPORATION
International Classes:
H03F3/18; H03F3/34; H03F3/45; (IPC1-7): H03F3/45; H03F3/34
Domestic Patent References:
| JP3121512A | ||||
| JP1264406A | ||||
| JP1188111A | ||||
| JP5980007A |
Attorney, Agent or Firm:
Kaoru Furuya (2 outside)