Title:
MICROPROCESSOR
Document Type and Number:
Japanese Patent JPH07114475
Kind Code:
A
Abstract:
PURPOSE: To obtain a microprocessor capable of performing debug by external user interruption by returning a wait instruction to the same one even when debug interruption is performed while the wait instruction is being executed in a debug mode.
CONSTITUTION: This processor is equipped with a control means which holds the leading address of an instruction under execution and that of an instruction to be executed next in a PC register 12 and an NPC register 13, and saves the leading address held in the PC register 12 to a stack when the debug interruption is generated during the debug mode execution, and transfers a mode to the debug mode based on the leading address saved to the stack when it is returned from a debug acknowledge mode.
Inventors:
MIURA HIROMICHI
NAKANO NAOYOSHI
NAKANO NAOYOSHI
Application Number:
JP25873693A
Publication Date:
May 02, 1995
Filing Date:
October 15, 1993
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F11/28; G06F9/46; G06F9/48; G06F11/22; (IPC1-7): G06F9/46; G06F11/22; G06F11/28
Attorney, Agent or Firm:
Hiroaki Tazawa (1 person outside)
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