Title:
【発明の名称】自動等化方法及び自動等化器
Document Type and Number:
Japanese Patent JP3099796
Kind Code:
B2
Abstract:
An automatic equalizer comprises a transmission symbol sequence generation circuit 101, a parallel received signal estimation circuit 102, subtracters 103-1 through 103-6, absolute value squaring arithmetic circuits 102-1 through 104-6, adders 105-1 through 105-4, and a discriminator 106. Maximum likelihood estimation can be performed with simple operations by means of using added error signals given by adding square error signals obtained from estimated error signals for an N number of delayed received signals delayed by a time instant corresponding to 0 through (N-1) symbols, to select the transmission symbol sequence having the smallest error.
Inventors:
Yoshikazu Kakura
Kazuhiro Okanoue
Tomoki Ohsawa
Kazuhiro Okanoue
Tomoki Ohsawa
Application Number:
JP5266698A
Publication Date:
October 16, 2000
Filing Date:
February 19, 1998
Export Citation:
Assignee:
NEC
International Classes:
H03H15/00; H03H17/02; H03H21/00; H03M13/23; H04B3/04; H04B3/14; H04L25/03; (IPC1-7): H04B3/14; H03H15/00; H03H17/02; H03H21/00
Attorney, Agent or Firm:
Yasuo Suzuki (1 person outside)