Title:
【発明の名称】アース平衡のすぐれた過電圧過電流保護回路
Document Type and Number:
Japanese Patent JP2934502
Kind Code:
B2
Abstract:
An overvoltage and overcurrent protection for an exchange terminaL circuit which has two input terminals (a, b) and a number of output terminals (T1-T). The input terminals are connected to a two-wire line and the output terminals are connected to equipment for the transmission of analog as well as digital signals over the line via the exchange terminal circuit. The exchange terminal circuit comprises an impedance matching network having a transformer at the primary as well as secondary sides of which there are networks that are symmetric in respect to earth. The network at the primary side comprises two primary winding halves (L1, L2) between which a capacitor (C) is series connected. The novel features of the invention is a varistor (V1) that is connected in parallel with the capacitor (C). When a surge pulse has charged the capacitor to the rated voltage of the varistor the varistor goes conductive thereby increasing the current through the primary winding until the core of the transformer is saturated. At the secondary side of the transformer there is a varistor (V2) and Zener diodes (Z5-Z8) which act to stepwise reduce the surge pulse as transformed to the secondary to a voltage which is safe for the connected equipment.
Inventors:
YAKI IBAN
Application Number:
JP50912491A
Publication Date:
August 16, 1999
Filing Date:
March 27, 1991
Export Citation:
Assignee:
TEREFUON AB ERU EMU ERIKUSON
International Classes:
H02H9/00; H02H9/02; H02H9/04; H04M11/00; H04M19/00; H04Q11/04; (IPC1-7): H02H9/00; H02H9/02; H02H9/04; H04M11/00; H04M19/00
Domestic Patent References:
| JP5887959A | ||||
| JP63211823A | ||||
| JP5917664U | ||||
| JP3819320Y1 | ||||
| JP59500544A |
Other References:
【文献】米国特許4539443(US,A)
Attorney, Agent or Firm:
Akira Asamura (2 outside)