PURPOSE: To reduce load capacity of a bit line, to reduce power consumption and to perform reading and writing at high speed by providing a switch circuit to divide a memory cell array and performing ON/OFF control in accordance with an address.

CONSTITUTION: Memory cell arrays 102, 108 are constituted with memory means which hold data of reading/writing, these memory means are selected by an output result of a row decoder 100 to which an address ADDR is inputted. A switch circuit 103 connects or separates bit lines of the inside of the memory cell arrays 102, 108 by ON/OFF operation, and divides the memory cell arrays 102, 108. A control circuit 107 generates a control signal CNT of the switch circuit 103 by making a part of an address ADDR as an input signal. Thereby, in writing and reading, since each bit line is cut off by a switch circuit, load capacity of bit lines is influenced by only the half of all memory cells. Therefore, reducing power consumption and increasing operation speed can be attained.