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Patent Searching and Data


Title:
MEMORY CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH0696111
Kind Code:
A
Abstract:

PURPOSE: To improve the throughput of a store instruction by performing the execution of the store instruction to increase/decrease an address at a fixed interval with a request pipe of a small metal quantity.

CONSTITUTION: At a vector processor 2, plural request pipes 20A0-20B1 to issue a memory request are provided at a main storage device 1. The request pipes 20A0-20A1 process the store instruction which increases/decreases the address at the fixed interval and smaller than the 1/2 block size of a buffer memory 30 in a scolar processor 3, and the request pipes 20B0-20B1 process all the store instructions. An instruction control part 21 selectively uses the request pipes 20A0-20B1 corresponding to the store instruction to increase/ decrease the address at the fixed interval and the other store instruction.


Inventors:
NUNOKAWA HIROHARU
ISOBE TADAAKI
KITAI KATSUYOSHI
YAZAWA SHIGEKO
Application Number:
JP4712192A
Publication Date:
April 08, 1994
Filing Date:
March 04, 1992
Export Citation:
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Assignee:
HITACHI LTD
HITACHI COMPUTER ENG
International Classes:
G06F17/16; (IPC1-7): G06F15/347
Attorney, Agent or Firm:
Kenjiro Take