Title:
【発明の名称】位相同期ループのための位相・周波数調整回路網および方法
Document Type and Number:
Japanese Patent JPH0744447
Kind Code:
B2
Abstract:
An improved multiple frequency digital phase-locked loop circuit 10 is described. The improved digital phase-locked loops utilizes a single circuit 12 to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal 30 with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The multiple frequency provides frequency adjustments by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controllable clock signal. The improved multifrequency digital phase-locked loop is suitable for use as a tone detector with the addition of a lock detector 22 wherein the phase-locked loop can be programmed for a plurality of known operating frequencies.
Inventors:
Rev Ain, Stephen N
Application Number:
JP50024584A
Publication Date:
May 15, 1995
Filing Date:
December 31, 1984
Export Citation:
Assignee:
Motro-La Inco-Pole-Ted
International Classes:
H03D13/00; H03K5/26; H03K5/00; H03K5/13; H03K5/22; H03K23/66; H03L7/00; H03L7/06; H03L7/085; H03L7/095; H03L7/099; H04L7/033; (IPC1-7): H03L7/06
Domestic Patent References:
| JP5129068A |
Attorney, Agent or Firm:
Shinsuke Onuki (1 person outside)
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