Title:
【発明の名称】積和演算処理方法およびその装置
Document Type and Number:
Japanese Patent JP3130797
Kind Code:
B2
Abstract:
In a multiplication process, an operation process applied to a multiplicand is changed in accordance with a selection command for an addition/subtraction selecting signal to generate partial products of a multiplier and the multiplicand, and the partial products and an augend/minuend are added together, thereby ensuring that an adder dedicated to addition/subtraction is unneeded, the circuit scale can be reduced and the operation can be carried out at a high speed.
Inventors:
Masahiro Tsubakihara
Application Number:
JP16739596A
Publication Date:
January 31, 2001
Filing Date:
June 27, 1996
Export Citation:
Assignee:
NEC IC Microcomputer System Co., Ltd.
International Classes:
G06F17/10; G06F7/52; G06F7/544; (IPC1-7): G06F17/10
Domestic Patent References:
| JP4246723A | ||||
| JP62229439A | ||||
| JP52128026A | ||||
| JP635673A | ||||
| JP4313157A | ||||
| JP566924A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)