【発明の名称】再構成可能なデュアル・プロセッサ・システム

Japanese Patent JP2552651

B2

A is a duel processor system (100) with duplicated memory (114,124) has two modes (10,11) of operation: a converged mode (10) in which one of the two processors (101,102) is active and executing all system tasks while the other processor is inactive; and a diverged mode (11) in which both processors are active and independently executing different tasks. The system automatically changes modes in response to requests such as manual and program control and certain system fault conditions. In diverged mode, the system may be in either of two states of operation (1 and 2). In one state (1) one processor (101) is designated a primary processor, and in the other state (2) the other processor (102) is designated the primary processor. In the converged mode the system may be in either of four states of operaton (3-6). In two of these states (3,4) one processor is active while the other processor is standing by ready to take up execution of tasks from the point where the one processor stoped execution. In the other two of these states (5,6) one processor is active while the other processor is out of service and cannot take up task execution without being initialized. The system 100 makes transitions between the various states in response to requests. Except for transitions of an active processor to an out-of-service condition, the state transitions are transparent to tasks other than fault recovery programs and, upon a fault condition, the faulted program.

BISHOTSUPU TOOMASU PATORITSUKU
BUTAUIRA JONASU
FUITSUCHI DEIUITSUDO JON
HANSEN ROBAATO KAARU
SHUMITSUTO DEIUITSUDO ANSONII
SAARATSUTO GUROOAA TEIMOSUI

JP50217085A

November 13, 1996

May 17, 1985

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EI TEI ANDO TEI CORP

G06F11/00; G06F11/16; G06F11/20; G06F15/16; G06F15/177; (IPC1-7): G06F11/20; G06F15/16

JP53104140A
JP57114961A
JP4875144A
JP5872267A

Masao Okabe (2 outside)

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