Title:
【発明の名称】スキャンパス回路
Document Type and Number:
Japanese Patent JP2638281
Kind Code:
B2
Abstract:
The scan path circuit includes N number of flip-flops connected in cascade to form a shift register. A first selector and a second selector are connected to each flip-flop to supply the data signal and the clock signal, respectively, to the flip-flop. The first selectors switch the individual data in the normal operation to the scan path test signal and the Q output signals during the test. During the test, the Nth second selector switches the clock signal in the normal operation to the scan path test signal and the second selectors up to the (N-1)th selector switch the clock signals in the normal operation to the clock signals from the output terminals of the next selectors. Thus, clock signals applied to the flip-flops are delayed with respect to those applied to the succeeding flip-flops by a time delay caused by the second selectors, so that the shift register operates reliably irrespective of any clock skew.
Inventors:
OZAKI HIDEHARU
Application Number:
JP27005190A
Publication Date:
August 06, 1997
Filing Date:
October 08, 1990
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G01R31/317; G01R31/3185; G06F11/22; G01R31/28; (IPC1-7): G01R31/28; G06F11/22
Domestic Patent References:
| JP63239688A | ||||
| JP63263480A |
Attorney, Agent or Firm:
Naotaka Ide