PURPOSE: To provide a test jig for obtaining correct test results without employing an IC socket accompanying inter-pin parasitic capacitance or inductance of lead having adverse effect on the test results while facilitating maintenance and operation.

CONSTITUTION: The test jig for integrated circuit comprises a second board 5 formed with an electrode pattern 6 matching with pin configulation of an integrated circuit to be tested on the surface and a POGO pin contact pattern 7 conducting through the board with the electrode pattern 6 on the rear surface thereof, and a first board 1 mounting external components or circuits for operating the integrated circuit to be tested and having POGO pins 2 coming into contact with the POGO pin contact pattern 7 on the second board 5. The POGO pins 2 on the first board 1 are brought detachably into contact with the POGO pin contact pattern 7 on the second board 5.