Title:
INSULATED GATE TYPE TRANSISTOR AND SOLID-STATE IMAGE PICKUP ELEMENT
Document Type and Number:
Japanese Patent JPH0823039
Kind Code:
A
Abstract:
PURPOSE: To provide a low-noise insulated gate type transistor which can be used for an analog-like purpose.
CONSTITUTION: A depression type MOS transistor is formed in a double gate structure consisting of a floating gate 27 and a control gate 28. An N-type inversion layer 25 is formed in its channel by implanting N-type impurities. The prescribed amount of electric charge is stored in the floating gate 27, the gate voltage, to be applied to the control gate 28, is compensated based on the quantity of charge stored in the floating gate 27, and the DpNMOS transistor is ON-OFF controlled by positive voltage.
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Inventors:
HAMADA MINORU (JP)
Application Number:
JP15394194A
Publication Date:
January 23, 1996
Filing Date:
July 05, 1994
Export Citation:
Assignee:
SANYO ELECTRIC CO
International Classes:
H01L27/148; H01L21/339; H01L21/8247; H01L27/115; H01L29/762; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L29/788; H01L29/792; H01L27/148; H01L29/762; H01L21/339
Attorney, Agent or Firm:
Hironobu Onda
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