Title:
RETICLE AND FORMATION OF VERNER FOR ALIGNMENT THEREOF
Document Type and Number:
Japanese Patent JPH0766113
Kind Code:
A
Abstract:
PURPOSE: To provide a reticle required for the exposing process in the fabrication of semiconductor device and to improve the method for forming a vernier required for alignment of reticle.
CONSTITUTION: The reticle for exposing a wafer having a plurality of chip forming regions comprises a shading region 11, a region 12 provided with a predetermined pattern for forming an LSI, and a region 13 corresponding to scribe lines, wherein a first vernier pattern 14 is formed at a predetermined position on the region 13 corresponding to scribe lines and a second vernier pattern 15 is formed at a position being overlapped at the time of step alignment.
Inventors:
TAKAO YUKIHIRO
Application Number:
JP21644093A
Publication Date:
March 10, 1995
Filing Date:
August 31, 1993
Export Citation:
Assignee:
SANYO ELECTRIC CO
International Classes:
G03F1/42; G03F9/00; H01L21/027; H01L21/301; (IPC1-7): H01L21/027; G03F1/08; G03F9/00; H01L21/301
Attorney, Agent or Firm:
Takuji Nishino
Next Patent: 磁気光学素子材料