Title:
【発明の名称】ゼロパワー電気的変更可能不揮発性ラッチ
Document Type and Number:
Japanese Patent JP2831015
Kind Code:
B2
Abstract:
A compact, nonvolatile, zero static power, electrically alterable, bistable CMOS latch device is fabricated with single layer of polysilicon. The single polysilicon layer forms the floating gates of the nonvolatile elements of the device. The control gates are formed in the substrate by burried N+ diffusions and are separated from their respective floating gates by a thin oxide dielectric. The circuit can be designed to power-up in a preferred mode even before any programming operation has been performed on it. Thereafter, the circuit is available to be programmed to either of its two stable states. After the programming operation is completed and the circuit is latched to one of its two stable states, the fields across the thin oxide dielectrics are minimal and virtually no read disturb condition exist. Thus, the latch also offers excellent data retention characteristics.
Inventors:
BIKURAMU KOSHIKU
ERUROI EMU RUSERO
ERUROI EMU RUSERO
Application Number:
JP1784989A
Publication Date:
December 02, 1998
Filing Date:
January 30, 1989
Export Citation:
Assignee:
NASHONARU SEMIKONDAKUTAA CORP
International Classes:
G11C17/00; G11C14/00; G11C16/04; G11C16/06; H01L21/8247; H01L27/10; H01L29/788; H01L29/792; H03K3/356; (IPC1-7): G11C16/04; G11C16/06
Domestic Patent References:
| JP61501356A | ||||
| JP5894227A | ||||
| JP644061A | ||||
| JP59162694A | ||||
| JP1500704A |
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)