Title:
【発明の名称】パルス位相差符号化回路とパルス発生回路との複合装置及びデジタル制御PLL装置
Document Type and Number:
Japanese Patent JP2900772
Kind Code:
B2
Abstract:
A pulse phase difference encoding apparatus comprises a delay circuit (52) which is constituted by a plurality of interconnected delay elements, to which an input signal (PA) is input and which sequentially outputs, from a plurality of connecting points of the delay elements, a plurality of delayed signals obtained by delaying the input signal by a delay period determined by the numbers of the delay elements. Several pulse phase difference encoding circuits (52, 54) to each of which a pulse signal (PB, PX) is input, and each of which detects a delayed signal corresponding to an input timing of the pulse signal (PB, PX) among the plurality of delayed signals output by the delay circuit (52), outputs position data representing a position of the delay element of the delay circuit which issues the delayed signal, and generates digital data (D0-D14) corresponding to a phase difference between the input signal (PA) and the pulse signal (PB, PX) by using the position data. The several pulse phase difference encoding circuits (54, 56) share the delay circuit (52) in generating the digital data.
Inventors:
YAMAUCHI SHIGENORI
WATANABE TAKAMOTO
WATANABE TAKAMOTO
Application Number:
JP32766993A
Publication Date:
June 02, 1999
Filing Date:
December 24, 1993
Export Citation:
Assignee:
DENSOO KK
International Classes:
G01R25/00; G01R25/08; G01R29/02; H03K3/03; H03K3/354; H03K5/00; H03K5/135; H03K5/26; H03L7/06; H03L7/085; (IPC1-7): H03L7/06; H03K3/354; H03K5/00; H03K5/26
Domestic Patent References:
| JP63305617A | ||||
| JP3220814A | ||||
| JP4351008A | ||||
| JP6216721A | ||||
| JP5102801A | ||||
| JP61152127A | ||||
| JP63105515A | ||||
| JP63202129A |
Other References:
【文献】米国特許5477196(US,A)
【文献】欧州特許出願公開660518(EP,A1)
【文献】欧州特許出願公開660518(EP,A1)
Attorney, Agent or Firm:
Adachi Tsutomu