Title:
【発明の名称】ESD保護手段を具備する集積回路
Document Type and Number:
Japanese Patent JP2002522906
Kind Code:
A
Abstract:
An integrated circuit provided with ESD protection means comprising a silicon-controlled rectifier whose n-well (WLL), if the substrate (SBSTR) of the integrated circuit is of the p-type, is connected to the VDD supply instead of to the bonding-pad (BP) to which electronic circuitry is connected. Consequently, the anode is only formed by the p+ diffusion (d4) in the n-well (WLL). Therefore, negative voltages are allowed at the bonding pad (BP) because the junction is not forward-biased. Thus, an ESD protection towards the VSS is obtained. Additionally, a PMOST (MP) is used as an ESD protection towards the VDD.
Inventors:
Schrader Hans You
Application Number:
JP2000564236A
Publication Date:
July 23, 2002
Filing Date:
July 29, 1999
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
H01L27/04; H01L21/822; H01L21/8234; H01L21/8238; H01L27/02; H01L27/088; H01L27/092; (IPC1-7): H01L21/8238; H01L21/822; H01L21/8234; H01L27/04; H01L27/088; H01L27/092
Domestic Patent References:
| JPH1140686A | 1999-02-12 | |||
| JPH04230072A | 1992-08-19 | |||
| JPH09181267A | 1997-07-11 | |||
| JPH09167829A | 1997-06-24 |
Attorney, Agent or Firm:
Susumu Tsugaru (1 person outside)