Title:
MANUFACTURE OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0669345
Kind Code:
A
Abstract:
PURPOSE: To fabricate a large-scaled integrated circuit by patterning an arbitrary layert by employing an improved stepper scanner apparatus, and exposing a portion not yet exsposed with a conventional on-wafer direct drawing pattern formation apparatus. CONSTITUTION: A stepper scanner apparatus is used. The Fig. illustrates exposure scannings 6-1, 6-2,..., 6-1, 6-1+1,... for each IC 8-K on a substrate 12 including many ICs 8-1, 8-2,..., 8-k-1, 8-K, 8-K+1,... during manufacture. The apparatus is reconstructed such that it exposes most of the resist layers for defining a wiring pattern and interrupts the exposure at a location where wiring is arbitrarily altered. For the location exposure is executed with a conventional on-wafer direct drawing pattern formation apparatus in a later process. Hereby, a large- scaled integrated circuit is manufactured in which the number of integraged circuit logic units or devices per circuit is very large.
Inventors:
GUREN JIEI RIIDEII
Application Number:
JP2869793A
Publication Date:
March 11, 1994
Filing Date:
February 18, 1993
Export Citation:
Assignee:
GUREN JIEI RIIDEII
International Classes:
H01L21/82; G03F7/20; G11C29/00; H01L21/66; H01L23/525; (IPC1-7): H01L21/82
Attorney, Agent or Firm:
Shoichi Ui (3 others)
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