Title:
【発明の名称】データの伝送を同期化する方法およびシンクロナイザ
Document Type and Number:
Japanese Patent JP2804975
Kind Code:
B2
Abstract:
A synchronizer (24) is operable in a variety of modes. In a Master/Slave mode the synchronizer receives synchronizing clock signals from a device to which it is a "slave" and generates therefrom synchronizing clock signals to a device to which it is a "master". In a Slave/Slave mode the synchronizer receives synchronizing clock signals from two devices to which it is a slave. In this mode the synchronizer can buffer misalignment between the clocks and report their phase difference for corrective action. In a Slave mode, the synchronizer only receives a synchronizing clock signal. A data-routing multiplexer is employed in conjunction with the synchronizer which allows five devices to be connected to the synchronizer. Signals may be routed between any of the devices. Buffers internal to the data-routing multiplexer perform the frame alignment function.
Inventors:
Marl El Miller
Dale e garlic
Dale e garlic
Application Number:
JP26519888A
Publication Date:
September 30, 1998
Filing Date:
October 20, 1988
Export Citation:
Assignee:
Advanced Micro Devices Incorporated
International Classes:
H04J3/00; H04J3/06; H04L5/22; H04L7/00; H04Q5/00; H04Q11/04; (IPC1-7): H04L12/02; H04J3/00; H04L7/00
Domestic Patent References:
| JP5148232A | ||||
| JP62235847A | ||||
| JP6230447A | ||||
| JP6148256A |
Attorney, Agent or Firm:
Fukami Hisaro (2 outside)