PURPOSE: To provide the multiplier which can perform relatively fast processing with a relatively small hardware quantity.

CONSTITUTION: Circuits for respective digits consist of adders 1a, 1b, 1c, and 1d, 1st D flip-flops 3a, 3b, 3c, and 3d which propagate the respective digits of a multiplier while latching them in synchronism with a clock CLK, 2nd D flip-flops 2a, 2b, 2c, and 2d which latch either of the addition results of the adders for their digits or the addition results of the adders for next digits in synchronism with the clock CLK according to the values that the 1st D flip-flops 3a, 3b, 3c, and 3d latch, and delay circuits 5a, 5b, and 5c which delay the propagation of the clock CLK to next digits until the adders 1a, 1b, 1c, and 1d for the respective digits output carries, namely, until the adding operation is completed.