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Title:
IC CARD AND MEMORY ACCESS CONTROL METHOD FOR IC CARD
Document Type and Number:
Japanese Patent JP2003122646
Kind Code:
A
Abstract:

To quickly solve the problem of mismatching of memory regions when a power source is interrupted during processing in the rewriting of data and garbage collection.

A memory managing part 3 manages a memory part 2 by using a leading unit for managing a logical address and a data unit for managing data rewriting. The leading unit is provided with the logical address of the data unit and the physical address of the leading unit of the data unit, and the data unit is provided with the physical address of the next data unit of its own unit and state information indicating whether its own units is in the middle of writing and real data. As for restoration processing, the progress situation of the processing is detected by making the logical address and physical address of the memory part correspond to each other by the leading unit and the data unit, and the overwriting processing of data is executed only to the data unit in the middle of writing the state information. Even when a power source is interrupted during the garbage collection processing, the garbage collection processing is executed only to the unit in the middle of rewriting.


Inventors:
Yoshida, Kazu
Suzuki, Katsuhiko
Hirata, Shinichi
Goromaru, Hideki
Application Number:
JP2001000319081
Publication Date:
April 25, 2003
Filing Date:
October 17, 2001
Export Citation:
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Assignee:
NIPPON TELEGR & TELEPH CORP
International Classes:
G06F12/16; G06F12/00; G06K17/00; G06K19/073; G06F12/16; G06F12/00; G06K17/00; G06K19/073; (IPC1-7): G06F12/16; G06F12/00; G06K17/00; G06K19/073



 
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