PURPOSE: To prevent the malfunction of a memory element, to realize a stable operation to the noise of a power source and to reduce the number of components by providing the input terminal of a control signal and a control circuit in the memory element or an external circuit.

CONSTITUTION: When the control signal, the inverse of CTL goes to 'L', all the outputs of the control circuit 41 go to 'H' even when the control signals, the inverse of OE, the inverse of WE, the inverse of CE are situated in any state, a memory is not selected to be fixed to an inoperative state. Thereby, all the inputs of a reading signal, the inverse of OE, a writing signal, the inverse of WE, a chip selecting signal, the inverse of CE are invalidated. When the signal, the inverse of CTL goes to 'H', AND gates 412W414 are opened through an inverter 411 and when the signals, the inverse of OE, the inverse of WE, the inverse of CE go to 'L', they are inputted to a control logic 43 to select the operation mode of the memory 46.