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Patent Searching and Data


Title:
IC PACKAGE
Document Type and Number:
Japanese Patent JPH04184954
Kind Code:
A
Abstract:

PURPOSE: To enhance the reliability upon the connection for making the title IC package applicable to multiple pins by a method wherein the conductor circuits connecting the electrodes on IC chips with lead frames are made on the resin parts on the surface almost flush with the electrode surface of the IC chips and then sealed with a covering resin.

CONSTITUTION: The electrode formation surfaces of lead frames 6 and an IC chip 1 and the surface of a resin 2 between the former surfaces are made almost flush with one another. Next, conductor circuits 4 are made so as to connect the electrodes 3 on the chips 1 with the connecting terminals of the lead frames 6. Furthermore, the circuits 4 and the chips 1 on the exposed resins 2 are covered with another resin 5. Through these procedures, the deformation.short- circuit of the circuits 4 can be made hardly occur for enhancing the reliability upon the connection simultaneously facilitating the manufacture of the lead frames 6 thereby enabling the title IC package applicable to multiple pins to be manufactured.


Inventors:
OFUSA TOSHIO
TOKI SOTARO
Application Number:
JP31486190A
Publication Date:
July 01, 1992
Filing Date:
November 20, 1990
Export Citation:
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Assignee:
TOPPAN PRINTING CO LTD
International Classes:
H01L21/60; (IPC1-7): H01L21/60