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Patent Searching and Data


Title:
IIL-TYPE SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5481785
Kind Code:
A
Abstract:

PURPOSE: To improve dielectric strength by providing the buried layer of an I2L transistor to the boundary part between the 1st and 2nd epitaxial stacked layers grown on a semiconductor substrate and the buried layer of a bipolar transistor to the boundary part between the substrate and 1st epitaxial layer.

CONSTITUTION: On P-type semiconductor substrate 1, N+-type 1st buried layer 2 is diffusion-formed as the collector of a bipolar transistor, and on the entire surface, N- type 1st epitaxial layer 3 is grown while buried layer 2 is diffused again at the same time to flow partially in layer 3. Next, N+-type 2nd buried layer 2a as the emitter of an I2L transistor is diffusion-formed and on it, N-type 2nd epitaxial layer 3a is grown, but buried layer 2a flows as well. In an ordinary way afterward, P-type isolation region 4, P-type injector 5, P-type 1st and 3rd regions 6 and 8, and N+- type 2nd, 4th and 5th regions 7, 9 and 10 are formed and an internal wiring is provided, thereby obtaining an IC.


Inventors:
YOSHIZAWA MASAO
SUGANO HIROSHI
Application Number:
JP15025477A
Publication Date:
June 29, 1979
Filing Date:
December 13, 1977
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/8226; H01L27/02; H01L27/082; H03K19/091; (IPC1-7): H01L27/08; H03K19/08