Title:
IMAGE LAYOUT PROCESSOR
Document Type and Number:
Japanese Patent JP2818066
Kind Code:
B2
Abstract:
PURPOSE: To provide the image layout processor which can simulate the layouts of graphics and line drawings on a block copy layout sheet on a display screen with good accuracy.
CONSTITUTION: Respective blank material data are read from a data input device 11 and are stored into an external memory device 12. A CPU 17 develops respective the blank material data on a bit map and store the graphic data and illustration mask data in respective plane memories 14a, 14b after data compression. The line drawing data is subjected to the extraction the outline of the line drawings after data compression and is stored into the plane memory 14c for the line drawings. The CPU 17 superposes contents of the memories 14a to 14c and displays the layout on a CRT 15. The illustration mask is positioned in accordance with the input instruction from an instruction input device 16 after the layout display.
Inventors:
Nakagawa Haruo
Murayama Hiroshi
Osamu Ikeda
Murayama Hiroshi
Osamu Ikeda
Application Number:
JP7871992A
Publication Date:
October 30, 1998
Filing Date:
February 27, 1992
Export Citation:
Assignee:
Dainippon Screen Mfg. Co., Ltd.
International Classes:
G03F1/00; G03G15/22; G06F17/50; H04N1/387; (IPC1-7): G03F1/00; G03G15/22; G06F17/50; H04N1/387
Domestic Patent References:
| JP63253473A | ||||
| JP239351A | ||||
| JP5730084A |
Attorney, Agent or Firm:
Tsutomu Sugitani