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Title:
IMAGE PROCESSING APPARATUS
Document Type and Number:
Japanese Patent JP2012124796
Kind Code:
A
Abstract:

To provide a signal processing apparatus includes a decoder circuit which reads out minimal fault information from volatile storage means having faulty pixel information temporarily stored therein and decodes the faulty pixel information in plural processing circuits using faulty pixel information having plural attributes differing in processing and purposes and a FIFO which stores position information out of the faulty pixel information temporarily therein.

Information directing correction of pixels (hereafter, faulty pixel information) includes information on a position in a photographed image of a pixel (hereafter, faulty pixel) which requires some kind of correction processing (hereafter, position information) and information on kind of correction (hereafter, ID information). The image processing apparatus includes a decode circuit which receives the faulty pixel information from volatile storage means which holds the faulty pixel information stored therein and decodes its contents, the configuration of which circuit is characterized in that the own position information from the ID information is kept stored in an internal FIFO of the decoder circuit, thereby making it possible to maintain a FIFO capacity without lowering the image processing throughput.


Inventors:
KATAGAWA HIROYASU
Application Number:
JP2010275262A
Publication Date:
June 28, 2012
Filing Date:
December 10, 2010
Export Citation:
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Assignee:
CANON KK
International Classes:
H04N5/232; G03B7/00; G03B17/00; G03B17/02
Attorney, Agent or Firm:
Yukio Takanashi



 
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