PURPOSE: To accelerate processing by enabling the simultaneous execution of plural sets of processing to be performed by connecting first and second buses selectively with a gate means.

CONSTITUTION: The processing by using a first data bus 4 and that by using a second data bus 10 can be executed independently or by interlocking them, respectively by connecting the first data bus 4 to the second data bus 10 with a first gate circuit 12 selectively. Especially, the storage of image information in image memory 3 and picture element density conversion processing at a magnification/reduction circuit 9 can be performed simultaneously. Also, the image information to which the picture element density conversion processing is applied by the magnification/reduction circuit 9 is outputted to a third data bus 14, and the processing by using the second data bus 10 and display processing by reading out the image information stored in buffer memory 13 can be performed in parallel. Thereby, the plural sets of processing can be performed simultaneously, which accelerates the processing.