To provide an image processor and an image processing method which realizes a high speed real time process in a simple constitution.

The image processor has a first to fourth write FIFOs 401-404 and a first to fourth read FIFOs ('FIFO block', hereinafter) for temporarily holding image data to be written and read in a data holding memory 118, and a memory access controller 409 for executing a requested access to the data hold memory 118 by the FIFOs 401-408. The processor comprises a write data controller 410 for always shifting the timing at which at least one FIFO among 401-408 requests the said access to the memory access controller 409 by a specified time from the timing at which other FIFOs among 401-408 request the access to the memory access controller 409.