To reduce memory capacity to be used to inversely quantize compressed image data in an image processor that decompresses the compressed image data which are subjected to progressive coding and divided into a plurality steps for transferring.
A a first scan component detection result memory 111 and a code bit memory 112 are provided as memories used by a digital signal processing circuit that can perform high-speed processing for each element unit. An inverse quantization circuit 102 converts compressed image data of this stage into inversely quantized data of the step on the basis of the first scan component detection result and code bits. An inverse DCT conversion circuit 104 applies inverse DCT conversion to the inversely quantized data of the step, and a superposition circuit 113 subsequently superimposes the inversely quantized data of the step on inversely DCT converted image data up to the previous step stored in an image data memory 114.
| JP3191462 | HIGH EFFICIENCY CODING DEVICE |
| WO/2020/060184 | IMAGE ENCODING/DECODING METHOD AND APPARATUS, AND RECORDING MEDIUM STORING BITSTREAM |
| JP2000152249 | IMAGE CODER |
KURODA MANABU
Hiroshi Koyama
Hiroshi Takeuchi
Yuji Takeuchi
Katsumi Imae
Tomoo Harada
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