Title:
IMAGE SIGNAL ENCODER AND IMAGE SIGNAL DECODER
Document Type and Number:
Japanese Patent JP3624457
Kind Code:
B2
Abstract:
PURPOSE: To improve efficiency for using a data bus by fixing the burst length of a storage means, storing plural kinds of image signals on the same row address while making column addresses different, and providing a memory control means for outputting a read command and successively designating the switching of plural column addresses.
CONSTITUTION: Plural kinds of image information are stored on the same row address while fixing the burst length of the storage means composed of a synchronous DRAM. Then, after the row address is designated by an active command, the read command is outputted plural times, the plural column addresses are successively switched and designated, and the image signals on the different column addresses are read out. Namely, the image signal for each frame is sent to frame memories 3 and 4 composed of SDRAM to be controlled by a memory control circuit 5. Then, the column address to read the frame memories 3 and 4 is switched for every two clocks and the data of a macro block to be read are sent to motion compensation circuits 7 and 8.
Inventors:
Satoshi Miyazawa
Application Number:
JP8299995A
Publication Date:
March 02, 2005
Filing Date:
April 07, 1995
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H04N5/907; H04N5/92; H04N5/937; H04N11/04; H04N19/102; H04N19/105; H04N19/134; H04N19/136; H04N19/137; H04N19/159; H04N19/167; H04N19/176; H04N19/186; H04N19/196; H04N19/423; H04N19/46; H04N19/50; H04N19/503; H04N19/51; H04N19/577; H04N19/593; H04N19/61; H04N19/625; H04N19/70; H04N19/91; (IPC1-7): H04N7/32; H04N5/907; H04N5/92; H04N5/937; H04N11/04
Domestic Patent References:
| JP7298264A |
Attorney, Agent or Firm:
Akira Koike
Eiichi Tamura
Seiji Iga
Eiichi Tamura
Seiji Iga
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