To decrease write clock jitter by suppressing variations of power (power supply ripple) to be supplied to a PLL circuit.

An image signal is modulated in an LD modulator 10, a light beam is generated by controlling a laser beam generator (LD) 11 using an output signal of the LD modulator 10, a photosensitive body is scanned by said light beam, and an electrostatic latent image is formed on said photosensitive body. A write clock synchronized with the image signal is generated by a write clock generating means 23 but a PLL circuit 30 is provided in said write clock generating means 23. A power supply regulating means 42 suppresses variations of power to be applied to said PLL circuit 30. Power is supplied to a VCO of the PLL circuit 30 via the power supply regulating means 42, thereby suppressing the variations of power to be supplied to the VCO of the PLL circuit, reducing write clock jitter (fluctuation of an oscillation frequency of the PLL), and attaining improvement of image quality.