Title:
改良型フラクショナル-N位相同期ループ
Document Type and Number:
Japanese Patent JP4713050
Kind Code:
B2
Abstract:
A phase-locked loop has a phase detector that generates a phase difference signal, a circuit that generates a phase-locked loop output signal having a frequency that is a function of the phase difference signal, a frequency divider that receives the phase-locked loop output signal and generates therefrom a divided frequency signal. To substantially reduce variation in the duty cycle of the divided frequency signal, a comparison signal having one half the frequency of the divided frequency signal is generated. This may be performed by configuring a latch to toggle its output state once for every cycle of the divided frequency signal. To compensate for the additional division by two in the feedback path, the phase detector may use a dual-edge triggered latch to generate the phase difference signal so that it represents a phase difference between the reference signal and a signal having twice the frequency of the comparison signal.
More Like This:
| JP2011120106 | CLOCK DATA RECOVERY CIRCUIT |
| JP2022148299 | OSCILLATION DEVICE AND TRANSMITTER PROVIDING THE SAME |
| JPS54151359 | PHASE COMPARATOR |
Inventors:
Nilsson, Magnus
Hagberg, Hans
Hagberg, Hans
Application Number:
JP2001564456A
Publication Date:
June 29, 2011
Filing Date:
February 28, 2001
Export Citation:
Assignee:
Telefon Akti Bora Get Elm Ericson (Pubble)
International Classes:
H03K5/26; H03L7/089; H03D13/00; H03K23/66; H03L7/183; H03L7/197
Domestic Patent References:
| JP8213900A | ||||
| JP9261048A | ||||
| JP11234100A |
Foreign References:
| WO1999048195A1 |
Attorney, Agent or Firm:
Yasunori Otsuka
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura