To minimize the required space regarding the geometry accelerator and to increase the speed by controlling branching between control units by defining a next address field during instruction execution.
A branching logic mechanism 102 includes a branching central logic mechanism 112 which is so constituted as to make a logical judgement of high level and individual control unit logical elements 115 which corresponding to respective control units 17 respectively. Each control logical element 115 is so constituted as to help its corresponding control unit 17 to execute conditional branching and make a logical judgement of low level for control over indirect address specification. Therefore, the efficient multipath logical branching is enabled, the complexity of logic regarding the geometry accelerator 23 of a graphic system is reduced, and the necessary storage space is minimized to increase its speed.
ROSSIN THEODORE G
STRUNK GLENN W
MCGRATH MICHAEL S
ROJAS EDMUNDO
TUCKER S PAUL
ASHBURN JON L
RAKEL TED
