Title:
回路内メモリ・アレイ・ビット・セル・スレシホルド電圧分布測定
Document Type and Number:
Japanese Patent JP4790110
Kind Code:
B2
Abstract:
An apparatus and method for operating a non-volatile memory including an array of bit cells. A selection is made between an operational power supply and a test power supply, the test power supply being on-chip programmable. The non-volatile memory is operated in a operational mode if the operational power supply is selected, and in a test mode if the test power supply is selected.
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Inventors:
Richard Kazuki Eguchi
David William Kurdimski
Thomas jue
David William Kurdimski
Thomas jue
Application Number:
JP2000350094A
Publication Date:
October 12, 2011
Filing Date:
November 16, 2000
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
G06F12/16; G01R31/28; G06F15/78; G11C29/12; G11C5/14; G11C16/02; G11C16/06; G11C29/00; G11C29/02; G11C29/50
Domestic Patent References:
| JP6012900A | ||||
| JP63229700A | ||||
| JP9320300A | ||||
| JP6176585A | ||||
| JP8297987A | ||||
| JP8077785A | ||||
| JP8315598A | ||||
| JP2001167588A | ||||
| JP2001266599A | ||||
| JP2000215700A | ||||
| JP1116999A | ||||
| JP2000173300A | ||||
| JP10241400A | ||||
| JP200090675A | ||||
| JP621194A | ||||
| JP11134317A | ||||
| JP11134884A | ||||
| JP11175501A |
Attorney, Agent or Firm:
Mamoru Kuwagaki