To provide a memory circuit which is hardly limited by the velocity of a memory tester.
Clock circuits 215, 217, which are linked together so as to receive a control signal having a first logical state and a second logical state, are provided. The clock circuits generates a first clock signal CLK in response to the first logical state and a second clock signal *CLK in response to the second logical state. The second clock signal has at least 2 times frequency of the first clock signal. An address counter 221 is linked so as to receive one of the first and second clock signals. The address counter generates sequences of address signals corresponding to one of the first and second clock signals. Arrays of a memory cell are arranged so as to generate sequences of data bits corresponding to the sequences of the address signals. Logical circuits 235, 239, 249 are linked together so as to receive sequences of the data bits. The logical circuits generate a logical combination of the sequences of the data bits.
| JPH05206797 | CLOCK SIGNAL GENERATING CIRCUIT |
| JPS60555 | GENERAL-PURPOSE MEMORY |
| JP2008041188 | SEMICONDUCTOR MEMORY DEVICE |
NORWOOD ROGER (US)
PENNEY DANIEL B (US)
