Title:
【発明の名称】信号位相装置
Document Type and Number:
Japanese Patent JP3067832
Kind Code:
B2
Abstract:
The input frames TRA, TRB of each channel, shifted in time, are each provided to a means of frame alignment (3, 4) on the basis of a low-frequency superframe signal, these means providing synchronising signals SYA, SYB, and to a common double memory (5) with cyclic addressing. This write addressing is such that each memory location contains a TRA block and a TRB block of like rank on the basis of write counters (7, 8) incremented by the signals SYA and SYB. The read counter (12) of each location is locked onto the most delayed signal out of the signals SYA and SYB by way of a phase comparator 9 and of a coincidence detector (13). The frames TRA' and TRB' output are in phase. Application to the masking of transmission errors.
Inventors:
Jen-Marc Bonnet
Jen-Eve Clair
Jen-Eve Clair
Application Number:
JP9419291A
Publication Date:
July 24, 2000
Filing Date:
April 24, 1991
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
H04J3/06; H04L1/02; H04L1/06; H04L1/22; H04L7/08; (IPC1-7): H04J3/06; H04L1/22; H04L7/08
Domestic Patent References:
| JP4866707A | ||||
| JP2186730A | ||||
| JP2192240A | ||||
| JP6450627A | ||||
| JP56114459A |
Attorney, Agent or Firm:
Tadahiko Ito (2 outside)