Title:
INFORMATION PROCESSING DEVICE AND INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2023146920
Kind Code:
A
Abstract:
To make it possible to acquire a signal required for analysis according to a generated error, as compared with a configuration for acquiring a signal from a fixedly set portion of a circuit in an FPGA.SOLUTION: An information processing device includes an FPGA device 10 that can reconfigure a logical circuit, performs data processing, acquires and outputs data of a signal from an acquisition target position set for a circuit portion for performing data processing when an error occurs in the data processing. A control unit 110 narrows down an analysis target according to a generated error. After outputting the data of the signal, the FPGA device 10 changes the acquisition target position in accordance with results of narrowing down the acquisition target position by the control unit 110.SELECTED DRAWING: Figure 4
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Inventors:
SASAKI HIROFUMI
Application Number:
JP2022054359A
Publication Date:
October 12, 2023
Filing Date:
March 29, 2022
Export Citation:
Assignee:
FUJIFILM BUSINESS INNOVATION CORP
International Classes:
G06F11/22
Attorney, Agent or Firm:
Jiro Furube
Fumio Ogata
Fumio Ogata