To secure the high reliability and fast responsiveness in a simple hardware constitution by adding a receiving means and an actuator control means to every actuator controller.
The controllers 101-A to 101-C receive the output signals from sensors 105 and 106 as the input data via the networks 121-A to 121-C. The processor cores 113-A to 113-C process the control information on an actuator device based on the processing programs stored in the memories 102A to 102C. Then the controllers 101-A to 101C carry out the actuator control instructions, and the cores 113-A to 113-C supply the control signals to the actuator devices 107 and 108 via the networks 121-A to 121-C. At the same time, the actuator control instruction decision circuits 104-A to 104-C monitor the signals 124-A to 124-C and perform the suppression interruptions when the control instructions are produced respectively.
KANEKAWA NOBUYASU
SATO YOSHIMICHI
HOTTA TAKASHI
