PURPOSE: To improve reliability and performance by adding information transfer mechanisms to respective information processors and connecting two information processors through the use of the information transfer mechanisms.

CONSTITUTION: Two information processors 5 and 6 are given, and they are constituted of arithmetic control processing mechanisms 20 and 21, storage mechanisms 30 and 31, bus control devices 40 and 41 and the information transfer mechanisms 1 and 2. The respective mechanisms are connected by internal buses 100 in the information processors. Since two information processors 5 and 6 are mutually connected by using the information transfer mechanisms 1 and 2, storage information of the storage mechanisms 30 and 31 in respective information processors 5 and 6 can be stored in the storage mechanisms of the information processor in the other system, and storage information in the storage mechanisms 30 and 31 can be maintained. Thus, high performance is attained without damaging high reliability.